1. Field of the Invention
The present invention generally relates to testing redundant word and bit lines in memory and, more particularly, to a method and apparatus for testing redundant word and bit lines during standard array built-in self-testing (ABIST).
2. Description of the Related Art
It is known to replace failed memory elements or lines in a memory array formed on a chip or substrate by the use of redundant memory elements or lines provided on the chip or substrate. The number of redundant word and bit lines depends on the size of the random access memory (RAM) in question. The larger the RAM, the higher the probability of word and bit lines being defective; therefore, the more advantageous it is to have redundant word and bit lines. Redundancy techniques generally use laser beams to blow fuses formed on the substrate at wafer level. In this manner, redundant elements are used to replace failing elements, thereby improving the yield of the product.
To lower the cost of making memories by reducing testing expenses and improving memory yields, systems have been disclosed which are self-testing and self-repairing. One such system, an array built-in self-test (ABIST) system, is disclosed in U.S. Pat. No. 4,939,694, which uses substitute address tables and error correction code techniques for correcting errors found in a memory cell. Other ABIST systems use one-dimensional and two-dimensional failed address registers to store word addresses of defective cells of a memory array. In other words, redundant lines are provided which extend in either one or two directions parallel to the word lines of the array.
In current designs, ABIST is used to test SRAM (static RAM) macros. Those macros that have redundancy also have a failed address register (FAR) associated with them. The FAR stores the addresses of failing word or bit lines. It also determines if the SRAM is still repairable by keeping track of the number of failing word or bit lines and the number of possible replacements. However, standard ABIST only test the normal word lines in the SRAM prior to fuse blow. During ABIST testing, the fails and failing addresses are loaded into the FAR. These failed addresses are then replaced by redundant word lines at fuse blow, and only after the fuses have been blown and the bad word lines replaced can the redundant word lines be tested by running ABIST once again.
In a young process, the SRAM will be tested at wafer level, the fuses blown to correct the failed word lines, and then retested. However, in a mature process, this is not always the case. The RAM might not be tested once again at wafer test but instead be placed in a module and then tested. If the redundant word lines were bad, then the module would have to be thrown away.
Off-chip testing is usually performed on all stand alone memories. Stand alone chips refer to strictly memory chips; e.g., 1 Megabyte (MB) SRAMs, 4 MB DRAMs (dynamic RAMs), and the like. Stand alone memories are testable with an off-chip tester because all inputs and outputs (I/Os) go off chip and are accessible by a tester. There are disadvantages associated with off chip testing, however. Off-chip testing takes longer to perform, and off-chip testing of very fast memories may be limited by the tester capability. Furthermore, off-chip testing is not possible for embedded memories since such memories do not have their I/Os going off chip and, therefore, cannot be accessed by the tester. An embedded memory is a memory having inputs and outputs coming from and going to logic blocks on the same chip such as a microprocessor. Since there is no access to the I/Os of embedded memories, some type of on-chip testing is required.
In light of the foregoing, there exists a need to allow for on-chip testing of the redundant word (and bit) lines during standard ABIST to determine whether the chip is repairable considering the number of normal word line fails as well as redundant word line fails.